MICROPROCESSOR CORE MEMORY SUBSYSTEM Russian patent published in 2013 - IPC G06F12/08 G06F9/30 

FIELD: information technology.

SUBSTANCE: memory subsystem which is connected to a central processing unit, a system controller, external memory and which includes cache memory, a set of data and instruction buffers, consisting of a stored data buffer, a write-back buffer, a downloaded data buffer, wherein the memory subsystem has additional stored data buffers, wherein the cache memory is two-layered, the first layer being connected to the central processing unit, the second-layer cache memory and the write-back buffer, and the second layer is connected to stored data buffers, the downloaded data buffer and the write-back buffer, wherein the buffer for stored data falling in the second-layer cache memory has parity bits for noiseless coding and is connected to the write-back buffer.

EFFECT: high efficiency of the device, high noise-immunity of the system and avoiding additional delays when reading and loading data.

3 cl, 1 dwg