FIELD: information technology.
SUBSTANCE: device has in each bit of a tetrad four AND elements, two OR elements, four logic inverters, two RS flip flops, coincidence adder, each tetrad has two code correction circuits for sum of tetrad sum, and a circuit for generating an extra carry digit.
EFFECT: simplification of the device and faster operation.
1 dwg, 2 tbl
| Title | Year | Author | Number |
|---|---|---|---|
| METHOD AND DEVICE FOR ADDING AND SUBTRACTING BINARY DECIMAL CODE | 2008 |
|
RU2389064C1 |
| BINARY-CODED DECIMAL SUMMATION METHOD AND DEVICE | 2008 |
|
RU2395833C2 |
| METHOD AND DEVICE FOR SUBTRACTING BINARY CODES | 2010 |
|
RU2410746C1 |
| METHOD AND DEVICE FOR ADDING BINARY CODES | 2008 |
|
RU2388041C2 |
| METHOD AND DEVICE FOR BINARY-CODED DECIMAL MULTIPLICATION | 2008 |
|
RU2386998C1 |
| COMBINATIVE ACCUMULATING ADDER | 2005 |
|
RU2292073C1 |
| METHOD AND APPARATUS FOR SUBTRACTING UNITS | 2014 |
|
RU2540787C1 |
| PULSE COUNTER | 2014 |
|
RU2551414C1 |
| PULSE COUNTING METHOD AND DEVICE | 2013 |
|
RU2538949C1 |
| PULSE COUNTER | 2010 |
|
RU2419200C1 |
