METHOD AND DEVICE FOR SPEED TESTING MULTIPORT MEMORY ARRAY Russian patent published in 2010 - IPC G11C29/34 

Abstract RU 2408093 C2

FIELD: information technology.

SUBSTANCE: method of testing a memory array in test mode involves the following: simultaneous writing a first data template on a first address into the memory array through a first write port and a second data template on a second address into the memory array through a second write port, where the first data template is different from the second data template, reading the first and second data templates from the memory array through at least a first read port, and simultaneous comparison of the first data template read from the memory array with the first data template written into the memory array on a first comparator and comparison of the second data template read from the memory array with the second data template written into the memory array on a second comparator which is different from the first comparator, in test mode: receiving a permanent data template at the data input of the first comparator.

EFFECT: cutting time for testing memory arrays.

20 cl, 4 dwg

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RU 2 408 093 C2

Authors

Krishnamurti Anand

Mamford Klint Uehjn

Mamileti Lakshmikant

Pehjtel Sandzhej B.

Dates

2010-12-27Published

2007-03-01Filed