METHOD FOR TESTING NON-VOLATILE MEMORY CHIPS AND DEVICE FOR ITS IMPLEMENTATION Russian patent published in 2024 - IPC G11C29/10 G06F11/26 

FIELD: testing non-volatile memory chips.

SUBSTANCE: invention relates to a method and device for testing non-volatile memory chips. In the method, Test 1, Test 2, Test 3, designed for testing non-volatile memory chips, are carried out selectively or sequentially after each other, at the end of each test, and the commands inside each test are executed in strict sequence: Test 1 is performed with the following sequence: C; ↑ (R1, S); ↓ (R0): the operation of erasing values in all memory cells, followed by the operation of reading memory cells in a straight sequence incrementally, and if the value of the cell is equal to logical 1, then the logical 0 is set to this cell, next comes the reading operation in the reverse sequence by decrement with the expectation of a logical 0 value; Test 2 is performed with the following sequence: C; ↑ (R1,S,R0); ↓ (R0): begins with the operation of erasing and setting logical 1, followed by the operation of reading memory cells from the beginning to the end incrementally from waiting for logical 1, after that each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and immediately read, then all cells are read in reverse order; Test 3 is performed with the following the sequence: C; ↑ (R1,S);C; ↓ (R1,S,R0); ↑ (R0), which begins with the erase operation, after that, read and set operations to 0 from the beginning to the end, followed by the operation of reading memory cells from the end incrementally with the expectation of a logical 1, after that, each cell from the first to the last is read, in case any of the cells have changed their values, it is set to logical 0 and immediately read, then all cells are read in direct order.

EFFECT: technical result is to expand the range of detection of defects in non-volatile memory.

4 cl, 4 dwg, 4 tbl