FIELD: information technology.
SUBSTANCE: content addressable memory circuit includes a plurality of lower-level match lines, a plurality of higher-level match lines and match line restoration circuitry. The lower-level match lines are configured to be restored to a pre-evaluation state during a pre-evaluation period. The higher-level match lines are configured to capture an evaluation state of respective groups of one or more of the lower-level match lines during an evaluation period and to be restored to a pre-evaluation state during the pre-evaluation period. The match line restoration circuitry is configured to prevent at least one of the lower-level match lines from being restored to the pre-evaluation state in response to corresponding enable information, e.g., one or more bits indicating whether match line search results are to be utilised.
EFFECT: low power consumption.
20 cl, 5 dwg
