FIELD: information technology.
SUBSTANCE: hard-decision bit from bits indicating the P-axial coordinate of a reception signal point is input into an area detection circuit, and based on the hard-decision bit input, the area detection circuit detects and outputs an area on the phase plane where the coordinate of the reception signal point is present. A soft-decision bit from bits indicating the coordinate of the reception signal point is input into a log-likelihood ratio (LLR) circuit, and based on the soft-decision bit input, the LLR circuit calculates a primary LLR. A LLR converter calculates the final LLR based on an output signal (area detection result) from the area detection circuit. In such a configuration, a log-likelihood ratio is calculated while limiting the scope within which the value of the log-likelihood ratio varies according to the position of the reception signal point, the interval between adjacent signal points including the hard-decision threshold of the bit.
EFFECT: log-likelihood ratio calculation at a higher rate while reducing the size of the circuit and consumed power, independent of the multilevel number of the modulation method.
22 cl, 17 dwg
