FIELD: information technology.
SUBSTANCE: invention discloses a system comprising a plurality of parallel processors on a single chip; computer memory on the chip and accessible to each of the processors. Each processor is designed to process a minimum set of instructions and has local cache memory circuits allocated to each of at least three specific registers in the processor. In another aspect, the invention provides a system having a plurality of parallel processors on a single chip; computer memory on said chip and accessible to each of the processors, wherein each of the processors is designed to process set of instructions which is optimised for parallel processing on the traffic level, and has access to the internal data bus of the computer memory on the chip, and the capacity of the internal data bus does not exceed that of one memory line.
EFFECT: faster command processing.
15 cl, 36 dwg
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