FIELD: physics.
SUBSTANCE: processor includes a decoding unit for receiving the indexed vector load instruction plus the arithmetic and / or logic (A/L) operation plus saving. The instruction is designed to indicate the source operand of the memory packed indexes, having a plurality of the memory packed indexes. The instruction also indicates the source operand of the packed data, having a plurality of the packed data elements. The processor also includes an execution unit coupled to the decoding unit. The execution unit, in response to the instruction, loads the plurality of the data elements from the memory cells corresponding to the plurality of the memory packed indexes, performs the A/L operations on the plurality of the packed data elements of the packed data source operand and the loaded plurality of the data elements, and saves the plurality of the result data elements in the memory cells corresponding to the plurality of the packed memory indexes.
EFFECT: provision of opportunities to improve the CPU performance.
25 cl, 29 dwg
