FIELD: information technology.
SUBSTANCE: apparatus for buffering data streams transferred between two interfaces which are RAM and CPU data buses, respectively, and having a buffer which is based on memory or registers and accumulates data for transmission thereof upon request from a second interface without accessing the first interface, wherein the apparatus has additional buffers, a tag controller and an output multiplexer, the tag controller being connected to a multiplexer, a buffer based on memory or registers and additional buffers for tracking relevancy of data stored therein, and buffer inputs of the apparatus are connected to RAM.
EFFECT: high efficiency of a memory subsystem, lying in shorter delay in obtaining data requested by a CPU, high flexibility of application and high carrying capacity of RAM data buses.
1 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| VIDEO CONTROLLER | 1991 |
|
RU2012043C1 |
| INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE | 2013 |
|
RU2662394C2 |
| ENFORCING STRONGLY-ORDERED REQUESTS IN WEAKLY-ORDERED PROCESSING SYSTEM | 2006 |
|
RU2405194C2 |
| MULTICHANNEL TELEMETERING SYSTEM FOR COLLECTING SEISMIC DATA | 2003 |
|
RU2244945C1 |
| HYBRID MICROPROCESSOR | 2014 |
|
RU2556364C1 |
| DEVICE FOR DEBUGGING PROGRAMS FOR MICROCOMPUTER | 0 |
|
SU1815643A1 |
| DATA ACQUISITION AND PROCESSING DEVICE | 2002 |
|
RU2218597C2 |
| METHOD AND DEVICE TO ESTABLISH CACHING POLICY IN PROCESSOR | 2008 |
|
RU2427892C2 |
| MICROPROGRAMMABLE COMPUTER INPUT/OUTPUT | 0 |
|
SU1667084A1 |
| RANDOM ACCESS MEMORY WITH HIGH EXTENT OF FAULT TOLERANCE | 2005 |
|
RU2327236C2 |
