FIELD: electrical engineering.
SUBSTANCE: substrate contains gate bus lines (G2, G3), auxiliary capacitor bus lines (CsYH3, CsYL.2), auxiliary capacitor bus line (Cs XH1) arranged within the same conductor layer as the gate bus lines (G2, G3) and forming the auxiliary capacitor (22) of the first subpixel (SP21) and auxiliary capacitor bus line (Csxl2) arranged within the same conductor layer as the gate bus lines (G2, G3) and forming the auxiliary capacitor (25) of the second subpixel (SP22). The auxiliary capacitor bus line (CsYH3) is connected to the auxiliary capacitor bus line (Csxh1); the auxiliary capacitor bus line (CsYL2) is connected to the auxiliary capacitor bus line (Csxl2) by means of conductors arranged within conductor layer other than that containing the gate bus lines (G2, G3).
EFFECT: ensuring the opportunity of accurate support of the substrate pixels potential.
10 cl, 10 dwg
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Authors
Dates
2013-07-27—Published
2009-11-05—Filed