FIELD: information technology.
SUBSTANCE: apparatus has in each binary bit one RS flip-flop, seven AND logic elements, five OR elements, four NOT elements, a data input, first and second data outputs and six control inputs. The method and apparatus for realising the method facilitate the execution of such logic operations as receiving a code in register flip-flops, code inversion for register flip-flops, an operation for shifting the received code to the left, a modulo 2 summation operation, logic addition of two binary codes and logic multiplication.
EFFECT: faster execution of elementary computational operations with minimal equipment costs.
7 cl, 1 dwg
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