FIELD: information technology.
SUBSTANCE: memory system in the recording method includes a memory controller and a memory device in which change data are received through the memory controller wherein the data are sent by a cache, and the change data are the data that is generated after the cache divides the first cache line to be written, and a cache line at the last level cache (LLC) into at least one data block, and which are used to indicate whether the data has changed in each of the at least one data block.
EFFECT: increased recording rate of reliable data.
16 cl, 6 dwg, 1 tbl
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|---|---|---|---|
| METHOD AND APPARATUS FOR CACHING VARIABLE LENGTH INSTRUCTIONS | 2007 |
|
RU2435204C2 |
| INSTRUCTION AND LOGIC FOR MEMORY ACCESS IN A CLUSTERED WIDE-EXECUTION MACHINE | 2013 |
|
RU2662394C2 |
| STORAGE DEVICE AND LEADING DEVICE | 2005 |
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RU2348992C2 |
| INTEGRATED CIRCUIT WITH MULTI-PORT SUPER MEMORY CELL AND CIRCUIT OF DATA TRANSFER ROUTE SWITCHING | 2010 |
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RU2481652C1 |
| SEMICONDUCTOR MEMORY UNIT | 1993 |
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RU2156506C2 |
| DATA PROCESSING DEVICE AND METHOD THEREOF | 1996 |
|
RU2182722C2 |
| MEMORY CONTROLLER, WHICH PERFORMS READING AND WRITING INSTRUCTIONS IN ORDER DIFFERENT FROM SIMPLE QUEUE | 1996 |
|
RU2157562C2 |
| COMPUTER SYSTEM AND METHOD FOR DATA TRANSMISSION IN COMPUTER SYSTEM | 1999 |
|
RU2220444C2 |
| CACHE-BASED TRACE RECORDING USING DATA OF CACHE COHERENCE PROTOCOL | 2018 |
|
RU2775818C2 |
| COHERENCE PROTOCOL AUGMENTATION TO INDICATE TRANSACTION STATUS | 2015 |
|
RU2665306C2 |
