MEMORY CONTROLLER, WHICH PERFORMS READING AND WRITING INSTRUCTIONS IN ORDER DIFFERENT FROM SIMPLE QUEUE Russian patent published in 2000 - IPC

Abstract RU 2157562 C2

FIELD: microprocessor computer system. SUBSTANCE: device may be used for memory control circuits of dynamic memory units with random access for sending writing instructions and resuming data processing without waiting for completion of writing instructions. Goal of invention is achieved by sent record buffer for dynamic memory units with random access. Sent record buffer has logical reading circuit, which allows reading access to records, which have been sent earlier and are under processing. Facilitated writing access buffer allows transmission of sent records to dynamic memory units with random access in order, which is different from simple queue, thus avoiding delays caused by sent records. This design results in possibility to change the order of processing for access requests of reading and writing cycles in page mode access computer system. EFFECT: increased speed of access to reading and writing cycles. 8 cl, 16 dwg

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RU 2 157 562 C2

Authors

Mout Randall

Dates

2000-10-10Published

1996-03-22Filed