METHOD OF DIGITAL CLOCK SYNCHRONIZATION Russian patent published in 2018 - IPC H04L9/36 G06K7/16 

Abstract RU 2640731 C1

FIELD: radio engineering, communication.

SUBSTANCE: based on the signals at the demodulator output the phases of the fronts of the received binary parcels, the values of which are converted into digital form, distribution histogram of the n phases of the binary parcel fronts is constructed based on the last n phases of the binary parcel fronts. Then in a sliding window of length k of successive phases of the parcel fronts, the area under the distribution histogram is counted, taking into account the cyclic numbering of phase readings of the fronts of the binary parcels. The received values of the areas below the histogram are compared together and the position of the sliding window is chosen in such a way that the maximum value of the area below the distribution histogram is achieved and the evaluation of phases of undistorted binary parcel fronts is considered the mean value of the phases of the binary parcel fronts of the sliding window of length k of successive parcel front phases with the maximum area below the distribution histogram. In this case, a decision is made about the presence of a signal in the communication channel with a monomodal distribution of the distribution histogram of the phases of the binary parcel fronts or its absence. And the length of the window from k of successive phases of binary parcel fronts are selected depending on the magnitude of the dispersion of the phase distribution of the fronts of the binary parcels.

EFFECT: increase in the accuracy and effectiveness of establishing the digital clock signals.

4 cl, 1 dwg

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RU 2 640 731 C1

Authors

Kvashennikov Vladislav Valentinovich

Dates

2018-01-11Published

2017-04-04Filed