FIELD: computer equipment.
SUBSTANCE: invention relates to pulse and computer equipment and can be used in construction of self-synchronizing trigger, register and computing devices, digital information processing systems. In circuit containing one inverter, four OR-AND-NOT elements and two AND-OR-NOT elements, second inverter, fifth OR-AND-NOT element are introduced, hysteresis trigger and additional inputs to the second, third and fourth OR-AND-NOR elements for feedback realization with output of hysteresis trigger, which combines outputs of the fourth and fifth OR-AND-NOR elements, and output of inverter, which input is connected to output of hysteresis trigger.
EFFECT: technical result consists in acceleration of interaction of D-flip-flop with source of its information input due to reduction of time, during which state of information input of D-flip-flop should not change after appearance of high level at its control input.
1 cl, 4 dwg
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