FIELD: physics; computer technology.
SUBSTANCE: invention concerns to pulse and computer technology and can use at construction of self-synchronous flip-flop, register and computing circuits, systems of digital information processing. This result is reached because the inverting element and four elements OR-AND-NOT are entered in the scheme containing two elements AND-OR-NOT, an information input, an operating input, direct and inverse information outputs and a display output are entered .
EFFECT: maintenance of self-synchronous realisation of the duple D flip-flop with high active level of a control signal, single-phase coding of an information input and paraphase coding of an information output.
7 cl, 8 dwg
| Title | Year | Author | Number |
|---|---|---|---|
| SELF-SYNCHRONISING TWO-CYCLE D FLIP-FLOP WITH LOW ACTIVE CONTROL SIGNAL LEVEL | 2007 |
|
RU2366080C2 |
| SELF-SYNCHRONISING TRIGGER WITH SINGLE-PHASE INFORMATION INPUT | 2008 |
|
RU2405246C2 |
| SELF-SYNCHRONIZING DYNAMIC TWO-STROKE D FLIP-FLOP WITH A SINGLE SPACER | 2018 |
|
RU2693319C1 |
| SELF-SYNCHRONISING SINGLE-STAGE D FLIP-FLOP WITH HIGH ACTIVE LEVEL OF CONTROL SIGNAL | 2007 |
|
RU2362266C1 |
| SELF-SYNCHRONIZING DYNAMIC TWO-STROKE D-FLIP-FLOP WITH ZERO SPACER | 2018 |
|
RU2693321C1 |
| SELF-SYNCHRONISING SINGLE-STAGE D FLIP-FLOP WITH LOW ACTIVE LEVEL OF CONTROL SIGNAL | 2007 |
|
RU2362267C1 |
| TWO-CYCLE SELF-CLOCKED RS FLIP-FLOP WITH PRESET AND CONTROL INPUT | 2008 |
|
RU2390093C1 |
| TWO-CYCLE SELF-CLOCKED RS FLIP-FLOP WITH PREST | 2008 |
|
RU2390923C1 |
| D-TRIGGER WITH SELF-SYNCHRONOUS PRESET | 2006 |
|
RU2319297C1 |
| SELF-SYNCHRONIZING DYNAMIC SINGLE-CYCLE D-FLIP-FLOP WITH ZERO SPACER | 2018 |
|
RU2693320C1 |
