FIELD: computer science and computer engineering.
SUBSTANCE: invention relates to technical means of computer science and computer engineering. A parallel adder-subtractor on neural logic elements contains: a number input unit, the first number register unit, a unit of switching and adders-subtractors, the second number register unit, a result register unit, a control unit, threshold and neuro-like elements. The new in the device is that arithmetic operations on the adder-subtractor are performed in a parallel format in direct codes, calculation of a modulo greater number is performed in subtraction of numbers by a switching scheme, transfer in addition and borrowing in subtraction of binary numbers are determined on a threshold element, neural and threshold logic elements are used.
EFFECT: increase in performance, reliability of operation, reduction in excessive hardware means, simplification of an operating algorithm of a control unit of a device.
1 cl, 10 dwg, 2 tbl
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Authors
Dates
2022-09-21—Published
2020-09-04—Filed