AND/AND-NOT TRIGGER LOGIC ELEMENT Russian patent published in 2023 - IPC H03K19/20 H03K19/09 H03K19/86 

FIELD: digital circuit engineering, automation engineering, industrial electronics.

SUBSTANCE: invention relates to digital circuit engineering, automation engineering and industrial electronics and, in particular, can be used in computer technology units built on logic elements. The AND/AND-NOT trigger logic element additionally contains two additional p-n-p-transistors, one additional n-p-n-two-emitter transistor and six additional resistors. The first additional resistor, the first additional p-n-p transistor and the second additional resistor are connected in series with each other. The common collector terminal of the first additional transistor and the second additional resistor is connected to the base of the third transistor. The base of the first additional transistor is connected to the common terminal of the third resistor and the collectors of the second and third transistors. A second additional p-n-p transistor and a third additional resistor are connected in series. The emitter of the second additional transistor is connected to the common terminal of the first additional resistor and the emitter of the first additional transistor. The base of the second additional transistor is connected to the common terminal of the first resistor and the collectors of the first and fourth transistors. The common terminal of the collector of the second additional transistor and the third additional resistor is connected to the base of the fourth transistor. The common output of the emitters of the fifth and sixth transistors is grounded. The base of the fifth transistor is connected to an additional fourth resistor. The base of the sixth transistor is connected to an additional fifth resistor. The free terminal of the additional fifth resistor is connected to the collector of the fifth transistor, the free terminals of the fourth and additional second resistors and their common output forms an inverting output of the logic element relative to the ground. The collector of the sixth transistor is connected to the free terminals of the fifth and additional third and fourth resistors and their common output forms a non-inverting output of the logic element relative to the ground. The outputs of the emitters of the additional n-p-n-two-emitter transistor form two inputs of the logic element relative to the ground. A sixth additional resistor is connected to the base of an additional n-p-n-two-emitter transistor. The free terminal of the sixth additional resistor is connected to the free terminal of the first additional resistor and the common terminal of the first and third resistors and the output of the supply voltage source. The collector of an additional n-p-n-two-emitter transistor is connected to the base of the first transistor.

EFFECT: increasing the output capacity of the trigger logic element AND/AND-NOT.

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