TRIGGER LOGIC ELEMENT OR/OR-NOT Russian patent published in 2023 - IPC H03K19/20 H03K19/09 H03K19/86 

FIELD: digital circuitry; automation; industrial electronics.

SUBSTANCE: invention can be used in computer technology blocks built on logical elements. Essence: the trigger logic element OR/OR-NOT contains nine transistors, ten resistors, a DC supply voltage source and a reference voltage source. What is new is that three additional transistors and five additional resistors are introduced, the first additional resistor, the first additional pnp transistor and the second additional resistor are connected in series, the free terminal of the first additional resistor is connected to the common terminal of the first, third resistors and the output of the power source, the common terminal of the collector of the first additional transistor and the second additional resistor is connected to the base of the fourth transistor, the base of the first additional transistor is connected to the collectors of the first, second and fourth transistors, the free terminal of the second additional resistor is connected to both the free terminal of the fourth resistor and the collector of the sixth transistor, and their common terminal forms a non-inverting output of the logic element relative to the "ground", the emitter of the sixth transistor is grounded, the second additional pnp transistor and the third additional resistor are connected in series, the emitter of the second additional transistor is connected to the common terminal of the first additional resistor and the emitter of the first additional transistor, the base of the second additional transistor is connected to the common the output of the third resistor and the collector of the third transistor, as well as to the collector of the fifth transistor, the common output of the collector of the second additional transistor and the third additional resistor is connected to the base of the fifth transistor, the free terminal of the third additional resistor is connected to both the free terminal of the fifth resistor and the collector of the third additional npn transistor and their common terminal forms the inverting output of the logic element relative to the "ground", the emitter of the third additional transistor is grounded, the fourth additional resistor is connected between the base of the sixth transistor and the common terminal of the third additional, fifth resistors, the collector of the third additional transistor and the inverting output of the logic element, the fifth additional resistor is connected between the base of the third additional transistor and the common terminal of the fourth, additional second resistors, the collector of the sixth transistor and the non-inverting output of the logic element.

EFFECT: increasing the load capacity of the trigger logic element OR/OR-NOT.

1 cl, 2 dwg