FIELD: data processing.
SUBSTANCE: invention relates to a method and a system for verifying the validity of the functioning of proprietary SF units placed in protected data storages. Method comprises a standard validation of the functioning of integrated circuit designs, comprising a design rule check (DRC), a layout comparison with a circuit (LVS), checking the extraction of parasitic resistors and capacitors (RC), checking the circuit simulation for functionality, checking the electromigration signal (EM), checking the voltage drop, checking the signal integrity (SI), verification of static synchronization, and subsequent placement of verified SF-units in protected data storage, according to the invention, preliminary extended control and verification of SF-units for mismatch of declared and executed characteristics, for presence of undocumented features are introduced, for presence of control marks, excluding repeated arrangement of data and corresponding versions and analogues, checking contacts by number, composition, type and purpose, comparison of files of graphic representation of GDS and LEF topologies with control graphic information—photographs and scans of topologies of products based on SF-blocks placed in storage, and after verification, data from the verification results relating to the analyzed SF units are transmitted for additional control of the proprietary SF units.
EFFECT: ensuring reliability of functioning of SF-units.
10 cl, 8 dwg
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Authors
Dates
2024-04-10—Published
2023-06-22—Filed