METHOD OF MATCHING STRUCTURES OF TOPOLOGY OF MICROELECTRONIC COMPONENT LAYER Russian patent published in 2024 - IPC G03F7/75 G06T7/10 G06N3/02 

FIELD: electricity.

SUBSTANCE: invention relates to lithographic processes. Technical result is achieved by steps of: obtaining the structure of the designed topology of the layer of the silicon wafer of the microelectronic component; obtaining at least one image of the surface of the manufactured silicon wafer of the microelectronic component; performing processing of at least one image using a machine learning model based on a neural network, trained to mark structures of a microelectronic component layer topology, forming at least one marked image of at least one structure of the topology of the microelectronic component layer; comparing at least one marked image of the structure of the topology of the layer of the manufactured silicon wafer of the microelectronic component with the structure of the designed topology of the layer of the silicon wafer of the microelectronic component; a set of images is formed, which contains at least one pair of images corresponding to the image of the structure of the projected topology of the layer of the silicon wafer of the microelectronic component and the image of the same structure on the image of the manufactured layer.

EFFECT: high accuracy of matching the structures of the topology of the microelectronic component layer with the structures of the topology of the designed layer.

11 cl, 13 dwg