FIELD: computer engineering.
SUBSTANCE: invention relates to computer engineering and specifically to an information storage device with high correcting capacity. In the disclosed solution, a memory unit, an input coding unit, AND, OR logic elements are provided, wherein a code which generates values of bits of the error syndrome is used: S=S4, S3, S2, S1, in which the bit values S2, S1 determine the number of the erroneous bit in the three-bit information unit, and the bit values s4, s3 determine the number of the information unit containing the error, presence of single values in bits S2, S1 and presence of zero values in bits S4, S3 indicates occurrence of single or double errors in check bits r1, r2, and presence of single values in bits S4, S3 and presence of zero values in bits S2, S1 testifies to occurrence of single or double errors in check bits r3, r4.
EFFECT: high fault-tolerance of the device.
1 cl, 1 dwg, 1 tbl
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Authors
Dates
2024-10-22—Published
2024-03-18—Filed