FIELD: calculating; counting.
SUBSTANCE: invention relates to computer engineering. Technical result is achieved by a processor with high reliability of operation, first and second encoding units which further comprise a third output, wherein the first coding unit generates the adjustment bit values at its first, second and third output by modulo 2 addition of information symbols coming from the first outputs of the logical operations and control unit to the inputs of the first coding unit, the second coding unit, generates control check digits values at the first, second and third outputs by modulo 2 summation of values of information symbols obtained during performance of arithmetic and logic operations and coming from the second outputs of the logical operation unit and control to inputs of the second encoding unit.
EFFECT: technical result consists in improvement of detecting ability of double errors in processor operation.
1 cl, 2 dwg
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