DEVICE FOR SUPPRESSION OF BACKGROUND NOISE Russian patent published in 1998 - IPC

FIELD: radio engineering. SUBSTANCE: device has serial circuit of unit measuring and averaging inter-period noise phase shift, unit, which calculates total noise phase shift, and function generator. In addition device has two channels each of which has first multiplier and serial circuit of second multiplier, adder and suppression filter. Output of first multiplier in each channel is connected to second input of adder. First inputs of first and second multipliers are connected in pairs and are connected to corresponding outputs of function generator. Unit measuring and averaging inter-period noise phase shift has serial circuit of dividing unit, function generator and logical unit, and two channels, each of which has accumulation unit, first multiplier and serial circuit of second multiplier, adder and averaging unit. First inputs of first and second multipliers in each channel are connected. Output of accumulation unit of first channel is connected to second inputs of first multipliers of both channels. Output of accumulation unit of second channel is connected to second inputs of second multipliers of both channels. Output of averaging unit of first channel is connected to first input of dividing unit and third input of logical unit. Output of first multiplier of one channel is connected to second input of adder of another channel. Goal of invention is achieved by introduced delay gate, which input is connected to corresponding input of unit measuring and averaging inter-period noise phase shift; and output is connected to second input of second multiplier of corresponding channel and two second input of first multiplier of another channel. Each channel of unit measuring and averaging inter-period noise phase shift has introduced memory unit which is inserted between output of accumulation unit and first input of first multiplier. Second claim of invention discloses device design in which accumulation unit has pulse generator and serial circuit of memory unit, adder, and AND gate, which second input is connected to clock input of memory unit and output of pulse generator. Output of adder is connected to information input of memory unit. Input and output of accumulation unit are respectively second input of adder and output of AND gate. Third claim of invention discloses device design in which averaging unit according to claim 1 has serial circuit of N delay gates, which outputs and input of first delay gate are connected to corresponding inputs of adder. Input and output of this unit are input of first delay gate and output of adder. EFFECT: decreased dynamic error.