FIELD: decoders. SUBSTANCE: input register 1 has n bits, which outputs are connected to corresponding information inputs of decoder 2, and two additional bits which outputs are connected to first and second inputs of "implication" logic gate, which output is connected to input of first delay gate 4 which output is connected to input for lock of decoder 2 and to input of second delay gate 5 which output is test output of device. Proposed functional connections increase reliability of output information signals due to lock of decoder 2. EFFECT: increased reliability. 1 dwg
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Authors
Dates
1994-01-30—Published
1990-08-08—Filed