MODULO 3 ADDER Russian patent published in 1994 - IPC

FIELD: computer technology; microelectronics. SUBSTANCE: adder has two bicondition gates, two modulo 2 addition elements, inputs of senior and junior digits of the first operand, inputs of senior and junior digits of the second operands, outputs of senior and junior digits of the result. Senior and junior digits x₁ and x₂ of the first operand X=2x₁+x₂ enter inputs of the adder, as well as senior and junior digits y₁ and y₂ of the second operand Y=2y₁+y₂, where x_i∈ {0, 1}, Y_i∈ {0, 1}, i= 1, 2 and X∈ {0,1,2,3}, Y∈ {0,1,2,3}. Two-digit binary code of result R=2z₁+r₂ is formed at outputs of the adder for operation of modulo 3 addition of two numbers X and Y. EFFECT: high speed of operation; simplified design. 1 tbl, 1 dwg