FIELD: computer engineering. SUBSTANCE: device has signal separation unit 1 and several identical decoding units 2. information output b and testing output c of signal separation unit serve as information and testing inputs for first decoding unit correspondingly. Each decoding unit i has information input which is connected to information register 2i which is connected to delay gate 3i which is connected to adder 4i. In addition decoding unit i has testing input which is connected to combination adder 5 and testing unit 6, corresponding output bits of information register 2i which belong to first decoding unit are connected to combination adder 5. Testing unit 6i has parity check switch 7, parity check register 8 and computing unit 10 which are connected in series and in bits. Computing unit 10 has switch 9. Bit outputs of parity check register 8 are connected to parity check switch 7. information output of i-th decoding unit is l output of adder 4i, which second input is connected to shift output of information register 2i. EFFECT: increased functional capabilities. 2 cl, 5 dwg
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Authors
Dates
1995-05-10—Published
1992-03-26—Filed