FIELD: electrical engineering. SUBSTANCE: for applying high positive or negative voltages across leads A of device, first p-channel transistor P1 and first n-channel transistor N1 are inserted in series between leads VH1 and VL1 for these respective voltages. Gates of both transistors are connected through load sections of transistors of respective other types of conductivity (N2, P3) to first and third input leads E1,E3. Gates of these transistors are connected to second and, respectively, fourth input leads E2, E3. First p-channel transistor and first n-channel transistor (P1, N1) are interlocked through load sections of transistors of respective polarity of conductivity P1, N3 inserted between gate leads and high positive or negative potential leads VH1, VL1; gates of these transistors are connected to output lead A. Output lead A may be placed at high positive or high negative potential depending on potential across input leads. EFFECT: improved design. 6 cl, 4 dwg
