FIELD: computer engineering. SUBSTANCE: storage device incorporating aggregate error detection and correction circuit has storage area divided into group of storage subareas. Each subarea has both standard storage cells and those for saving parity bits. Device also has groups of read amplifiers. Each amplifier group is connected to respective storage subarea. Aggregate error detection and correction circuit of device has each of these circuits used to correct standard bits included in storage data as well as output decoders. Each decoder is connected to output of respective error detection and correction circuit. When semiconductor storage device functions under normal conditions, only one of its subareas is invoked. When device operates in page-by-page mode, all subareas are invoked. EFFECT: reduced power requirement during data access under normal conditions. 2 cl, 6 dwg
