FIELD: semiconductor equipment. SUBSTANCE: device has load permission circuit for generation of permission signal during chip checking and permission of checking operation, circuit for application of load voltage for application of first load voltage and second load voltage in response to output signal of load permission circuit during checking operation, reading delay control circuit for reading first and second loading voltages and delaying operations of control circuit of reading amplifier during checking operation. During checking operation first and second load voltages are applied to adjacent digital buses in response to output signal of load permission circuit. Content of memory register which is selected by digital bus is read in response of output signal of reading delay control circuit. EFFECT: increased reliability. 12 cl, 7 dwg
