FIELD: automatic preliminary charge of line circuit. SUBSTANCE: device has multiple groups of memory units, buffer memory units for receiving gate signals for line and column address in order to provide data access in response to information about packet length and delay. In addition device has column address generator, time controller, packet end detector, generator of signal with data about packet and delay, packet and delay data detector, generator of preliminary charge signal. EFFECT: synchronous design. 8 dwg
