FIELD: computer engineering. SUBSTANCE: processor unit has first and second storage devices holding, respectively, first and second packed data. Each data pack includes first through fourth data items. Multiplying-and-adding circuit is coupled with first and second storage areas. This circuit incorporates first through fourth multipliers each receiving respective data. Multiplying-and-adding circuit also has first adder connected to first and second multipliers and second adder connected to third and fourth multipliers. Third storage area is coupled with adders and incorporates first and second fields for memorizing output data of first and second adders, respectively, as first and second data items of third data packs. EFFECT: improved efficiency with increased number of algorithms used. 37 cl, 48 dwg
Title |
Year |
Author |
Number |
METHOD, DEVICE AND COMMAND FOR PERFORMING SIGN MULTIPLICATION OPERATION |
2003 |
- Mejsi Vill'Jam V. Ml.
- Ngujen Kh'Jui V.
|
RU2275677C2 |
INTEGER-VALUED HIGH ORDER MULTIPLICATION WITH TRUNCATION AND SHIFT IN ARCHITECTURE WITH ONE COMMANDS FLOW AND MULTIPLE DATA FLOWS |
2003 |
- Ehjbel Dzhejms K.
- Uolterz Derin K.
- Tajler Dzhonatan Dzh.
|
RU2263947C2 |
PROCESSORS, METHODS, SYSTEMS AND COMMANDS WITH PACKED DATA ELEMENTS PREDICATION |
2014 |
|
RU2612597C1 |
COMMAND AND LOGIC OF PROVIDING FUNCTIONAL CAPABILITIES OF CIPHER PROTECTED HASHING CYCLE |
2014 |
- Gopal Vindokh
- Fegkhali Vazhdi K.
|
RU2637463C2 |
PROCESSORS, METHODS AND SYSTEMS FOR GAINING ACCESS TO REGISTER SET EITHER AS TO NUMBER OF SMALL REGISTERS, OR AS TO INTEGRATED BIG REGISTER |
2014 |
- Toll Bret L.
- Singal Ronak
- Gaj Baford M.
- Neik Mishali
|
RU2639695C2 |
DEVICE AND METHOD OF REVERSING AND SWAPPING BITS IN MASK REGISTER |
2014 |
- Uld-Akhmed-Vall Elmustafa
- Velentajn Robert
|
RU2636669C2 |
COMMANDS, PROCESSORS, METHODS AND SYSTEMS OF MULTIPLE REGISTERS ACCESS TO MEMORY |
2014 |
- Khinton Glen
- Toll Bret
- Singal Ronak
|
RU2636675C2 |
METHOD AND DEVICE FOR PARALLEL CONJUNCTION OF DATA WITH SHIFT TO THE RIGHT |
2002 |
- Sebot Dzhul'En
- Mejsi Vil'Jam, Ml.
- Debes Ehrik
- Ngujen Kh'Jui
|
RU2273044C2 |
THREE SOURCE OPERAND FLOATING POINT ADDITION PROCESSORS, METHODS, SYSTEMS AND INSTRUCTIONS |
2014 |
- Espasa Rokher
- Sole Gilem
- Fernandes Manel
|
RU2656730C2 |
MODULE FOR COPROCESSOR CACHE |
2011 |
|
RU2586589C2 |