PROCESSORS, METHODS AND SYSTEMS FOR GAINING ACCESS TO REGISTER SET EITHER AS TO NUMBER OF SMALL REGISTERS, OR AS TO INTEGRATED BIG REGISTER Russian patent published in 2017 - IPC G06F9/06 G06F9/30 

Abstract RU 2639695 C2

FIELD: physics.

SUBSTANCE: processor comprises a set of physical registers, each of which is configured to store the packed data; an executing link associated with a set of physical registers, wherein the executing unit is configured to access the set of physical registers using at least two different methods in response to instructions, wherein the mentioned at least two different methods include the first method in which a set of physical registers represents a number of N-bit logical registers; and the second method in which a set of physical registers represents one logical register of at least 2N bits, wherein the mentioned at least 2N bits are equal to at least 256 bits, wherein each of the instructions comprises an operation code and a dedicated field different from the operation code to indicate the method for gaining access to a set of physical registers for the specified command by the executing link.

EFFECT: reducing the area occupied by the registers on the crystal.

23 cl, 20 dwg, 35 ex

Similar patents RU2639695C2

Title Year Author Number
COMMANDS, PROCESSORS, METHODS AND SYSTEMS OF MULTIPLE REGISTERS ACCESS TO MEMORY 2014
  • Khinton Glen
  • Toll Bret
  • Singal Ronak
RU2636675C2
PROCESSORS, METHODS, SYSTEMS AND COMMANDS WITH PACKED DATA ELEMENTS PREDICATION 2014
RU2612597C1
COMMAND AND LOGIC OF PROVIDING FUNCTIONAL CAPABILITIES OF CIPHER PROTECTED HASHING CYCLE 2014
  • Gopal Vindokh
  • Fegkhali Vazhdi K.
RU2637463C2
PARTIAL WIDTH LOADING DEPENDING ON REGIME, IN PROCESSORS WITH REGISTERS WITH LARGE NUMBER OF DISCHARGES, METHODS AND SYSTEMS 2014
  • Rash Uilyam K.
  • Santiago Yazmin A.
  • Dikson Martin Gaj
RU2638641C2
PROCESSOR, METHOD, SYSTEM AND EQUIPMENT FOR VECTOR INDEXED MEMORY ACCESS PLUS ARITHMETIC AND / OR LOGIC OPERATIONS 2014
  • Ermolaev Igor
  • Toll Bret L.
  • Velentajn Robert
  • San Adrian Khesus K.
  • Doshi Gautam B.
  • Chakraborti Prasendzhit
  • Malladi Rama K
RU2620930C1
DEVICE AND METHOD OF REVERSING AND SWAPPING BITS IN MASK REGISTER 2014
  • Uld-Akhmed-Vall Elmustafa
  • Velentajn Robert
RU2636669C2
INTEGER-VALUED HIGH ORDER MULTIPLICATION WITH TRUNCATION AND SHIFT IN ARCHITECTURE WITH ONE COMMANDS FLOW AND MULTIPLE DATA FLOWS 2003
  • Ehjbel Dzhejms K.
  • Uolterz Derin K.
  • Tajler Dzhonatan Dzh.
RU2263947C2
MODULE FOR COPROCESSOR CACHE 2011
  • Dzhkha Ashish
RU2586589C2
DELAY-INSENSITIVE BUFFER FOR COMMUNICATION WITH ACKNOWLEDGEMENT 2014
  • Dosi Khem
  • Radzhu Anand
RU2598594C2
THREE SOURCE OPERAND FLOATING POINT ADDITION PROCESSORS, METHODS, SYSTEMS AND INSTRUCTIONS 2014
  • Espasa Rokher
  • Sole Gilem
  • Fernandes Manel
RU2656730C2

RU 2 639 695 C2

Authors

Toll Bret L.

Singal Ronak

Gaj Baford M.

Neik Mishali

Dates

2017-12-21Published

2014-06-26Filed