FIELD: physics.
SUBSTANCE: processor comprises a set of physical registers, each of which is configured to store the packed data; an executing link associated with a set of physical registers, wherein the executing unit is configured to access the set of physical registers using at least two different methods in response to instructions, wherein the mentioned at least two different methods include the first method in which a set of physical registers represents a number of N-bit logical registers; and the second method in which a set of physical registers represents one logical register of at least 2N bits, wherein the mentioned at least 2N bits are equal to at least 256 bits, wherein each of the instructions comprises an operation code and a dedicated field different from the operation code to indicate the method for gaining access to a set of physical registers for the specified command by the executing link.
EFFECT: reducing the area occupied by the registers on the crystal.
23 cl, 20 dwg, 35 ex
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