FIELD: computer engineering.
SUBSTANCE: group of inventions relates to computer technology and can be used for floating point addition. Processor of an aspect includes a decode unit to decode a three source floating point addition instruction indicating a first source operand having a first floating point data element, second source operand having a second floating point data element, and a third source operand having a third floating point data element. Execution unit is coupled with the decode unit and stores a result in a destination operand indicated by the instruction. Result includes a result floating point data element that includes a first floating point rounded sum, which represents an additive combination of a second floating point rounded sum and the third floating point data element. Second floating point rounded sum represents an additive combination of the first floating point data element and the second floating point data element.
EFFECT: technical result is increased productivity.
25 cl, 30 dwg, 5 tbl
