COMMANDS, PROCESSORS, METHODS AND SYSTEMS OF MULTIPLE REGISTERS ACCESS TO MEMORY Russian patent published in 2017 - IPC G06F9/30 

FIELD: physics.

SUBSTANCE: processor contains a plurality of N-bit registers; a decoding unit configured to receive a command to access the memory of a plurality of registers. The command to access the memory of a plurality of registers indicates a memory location and specifies a register; and a memory access unit coupled to the decoding unit and to the said plurality of N-bit registers. The memory access unit is configured, in response to the memory access instruction, of a plurality of registers to execute a memory access operation of a plurality of registers. The memory access operation of the plurality of registers includes using its own set of N-bit data in each of the said plurality of N-bit registers containing the specified register, which is the register, from which the data are loaded, or the register, in which the data are stored, and various corresponding N-bit sections in M×N-bit memory line corresponding to the specified memory location.

EFFECT: providing the ability to store large operands without the need to increase the physical register capacity.

24 cl, 21 dwg