FIELD: electrical communications; frame alignment receivers of digital message transfer systems.
SUBSTANCE: device has sync pulse identifier whose main output is connected to first input of adder and output, to signal input of shift register unit, main output of the latter being connected to second input of adder and additional output, to signal input of resolving unit; output of this resolving unit is connected to reset inputs of shift register unit and frame pulse shaper; clock input of sync pulse identifier is integrated with those of resolving unit, distorted sync character counter, frame pulse shaper, counter, and AND gate; control input of resolving unit is connected to output of threshold selection unit; counter output is connected to reset input of flip-flop whose setting input is connected to output of frame pulse shaper; output of the latter is connected to control input of distorted sync character counter; flip-flop output is connected to reset input of counter and to second input of AND gate whose output is connected to clock input of counter, output of the latter being connected to control inputs of threshold selection unit and maximal response weight selection unit, as well as to reset input of distorted sync character counter; data input of the latter is connected to additional output of sync signal identifier; output of distorted sync character counter is connected to address inputs of threshold selection unit and maximal response weight selection unit whose output is connected to control input of sync signal identifier. Signal input of the latter, clock input of frame pulse shaper, and output of frame pulse shaper function as signal input, clock input, and output of device, respectively. Novelty is introduction of distorted sync character counter, AND gate, flip-flop, and maximal response weight selection unit in device and assembly of sync signal identifier from shift register, sync group error detector, and sync signal response weight shaper with weighting coefficients shaped at output of the latter depending on number of errors in received sync groups.
EFFECT: enhanced noise immunity and speed.
1 cl, 4 dwg
Title | Year | Author | Number |
---|---|---|---|
DEVICE FOR CYCLIC SYNCHRONIZATION | 2005 |
|
RU2284665C1 |
DEVICE FOR CYCLIC SYNCHRONISATION | 2007 |
|
RU2348117C1 |
CYCLE SYNCHRONIZATION METHOD FOR SIGNALS WITH A CYCLE CONCENTRATED OR DISTRIBUTED SYNCHROGROUP | 2021 |
|
RU2780048C1 |
CYCLIC SYNCHRONIZATION DEVICE | 2021 |
|
RU2782473C1 |
FRAME SYNCHRONIZATION DEVICE | 2003 |
|
RU2231228C1 |
CODE PATTERN SYNCHRONIZATION DEVICE | 2023 |
|
RU2812335C1 |
CODE PATTERN SYNCHRONIZATION DEVICE | 2023 |
|
RU2810267C1 |
DEVICE FOR SYNCHRONIZATION BY CYCLES | 2005 |
|
RU2280956C1 |
CYCLE SYNCHRONIZATION DEVICE | 0 |
|
SU1172052A1 |
DEVICE FOR RECEIVING RELATIVE PHASE TELEGRAPHY SIGNALS WITH INCREASED IMMUNITY | 2020 |
|
RU2752003C1 |
Authors
Dates
2004-11-10—Published
2002-11-26—Filed