FIELD: computer engineering; data processing devices; reduced instruction set microprocessor systems.
SUBSTANCE: cache memory reading device contains address forming unit, pipeline latches 1A, 1B, 2A, 2B, address conversion unit, data memory, tags memory, comparison unit, control unit with two outputs, and timing pulse generator with two outputs.
EFFECT: increased performance of pipeline microprocessor system with reduced instruction set, reduced time of cache hit flag generation, and reduced power consumption.
4 dwg
| Title | Year | Author | Number |
|---|---|---|---|
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|
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RU2490696C1 |
