FIELD: physics.
SUBSTANCE: invention concerns digital calculation technics and can be applied in integrated circuits as a logical processor of multidigit binary data. The device includes k comparator blocks (1), n convolution blocks (2) and an output block (3). Each comparator block 1 contains three p-type pre-charge transistors (4-6) and m logical elements in the form of single-digit comparator element with six n-type transistors (9-14), while each convolution block (2) contains three pre-n-type charge transistors (15-17) and k/n second type transistor sections (18) with three p-type logical transistors (19-21), and an output block (3), which in its turn contains three p-type transistors (22-24), and n first type transistor sectors (25) of three n-type output transistors (26-28) according to the number of convolution blocks. Comparator block outputs (33-34) are connected to the similar inputs (43-45) of respective transistor sectors (18) of convolution blocks (2), the outputs of which (47-49) are connected to the similar inputs (51-53) of respective first type transistor sectors (25) of the output block (3).
EFFECT: faster operation during multidigit operand comparison.
4 dwg
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