CLOCKED LOGIC ELEMENT Russian patent published in 2011 - IPC H03K19/948 

FIELD: information technology.

SUBSTANCE: clocked logic element has a pre-charge p-type transistor, an n-type clock transistor, a p-type clock transistor, a p-type feedback transistor, an n-type switching transistor, a p-type switching transistor, a CMIS inverter, a logic unit having switching circuits consisting of series-connected n-type transistors whose gates are connected to logic inputs of the of the element. The pre-charge transistor is connected between the power bus and the first lead of the switching circuits, the second lead of which is connected through the clock transistor to the earthing bus. The clock transistor is connected between the power bus and the second lead of the switching circuits. Switching transistors are connected in parallel between the first lead of the switching circuits and the input of the CMIS inverter, the output of which is the output of the device and is additionally connected to the gate of the feedback transistor which is connected between the power bus and the input of the CMIS inverter. The gates of the pre-charge transistor, clock transistors and the switching transistor are connected to a clock bus, and the gate of the switching transistor is connected to the second lead of the switching circuits.

EFFECT: simplification of the device.

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