FIELD: computer engineering.
SUBSTANCE: proposed device has NAND gates 1-3 with outputs 10-12, logic gates of first polarity of conductivity 4 and of second polarity of conductivity 5, clock transistors 6, 7, pre-charge transistor 8, power bus 9, neutral bus 13, clock bus 14, variable signal inputs 15-17, device outputs 21, 25, 26, 29, 32, as well as p transistors 18-20, 22-24 and n transistors 27, 28, 30, 31, 33. Such device implements five logic functions of six variables, including 2AND-OR, 2OR-AND, 2AND, 4AND, and 6AND. Other set of five logic functions can be implemented across same outputs of device by connecting p transistor gates of logic gates 4, 5 to outputs of NAND gates 1-3. NAND gates 1-3 may have more than two inputs and a few parallel-connected key circuits allowing for implementing multifunction logic device using great number of input variable signals.
EFFECT: enlarged functional capabilities.
1 cl, 1 dwg
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