MULTI-INPUT LOGICAL "AND" ELEMENT ON CMOS TRANSISTORS Russian patent published in 2008 - IPC H03K19/94 H03K19/17 H03K19/20 

FIELD: computer engineering, possible use in MOS integration circuits during realization of logical devices.

SUBSTANCE: device contains AND-NOT element (1), inverting element (2), clock transistors (3) and (4) of n-type and p-type respectively, additional transistor (5) of n-type. The AND-NOT element (1) contains pre-charge transistor (6) of p-type and key circuit (7), made on serially connected transistors of n-type, gates of which are connected to inputs (8) of device. Pre-charge transistor (6) is coupled between power bus (9) and output (10) of AND-NOT element (1). First contact (11) of key circuit (7) of AND-NOT element (1) is connected to output (10) of AND-NOT element (1), and second contact (12) through clock transistor (3) is connected to zero bus (13), clock transistor (4) is coupled between power bus (9) and second contact (12) of key circuit (7). Gates of clock transistors (3,4) and pre-charge transistor (6) are connected to clock bus (14). Inverting element (2) contains logical transistor (15) of p-type, coupled between power bus (9) and output (16) and pre-charge transistor (17) of n-type, coupled between output of device and zero bus, gates of transistors (15,17) of inverting element (2) are connected respectively to output (10) and to second output (12) of key circuit (7). Additional transistor (5), gate of which is connected to output (16) of device, is coupled between output (10) of device and second output (12) of key circuit (7).

EFFECT: increased speed of device operation.

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