DIGITAL SIGNAL PROCESSORS WITH CONFIGURABLE BINARY MULTIPLIER-ACCUMULATION UNIT AND BINARY ARITHMETIC-LOGICAL UNIT Russian patent published in 2008 - IPC G06F9/30 G06F7/57 

FIELD: physics; computer technology.

SUBSTANCE: present invention pertains to digital signal processors with configurable multiplier-accumulation units and arithmetic-logical units. The device has a first multiplier-accumulation unit for receiving and multiplying the first and second operands, storage of the obtained result in the first intermediate register, adding it to the third operand, a second multiplier-accumulation unit, for receiving and multiplying the fourth and fifth operands, storage of the obtained result in the second intermediate register, adding the sixth operand or with the stored second intermediate result, or with the sum of the stored first and second intermediate results. Multiplier-accumulation units react on the processor instructions for dynamic reconfiguration between the first configuration, in which the first and second multiplier-accumulation units operate independently, and the second configuration, in which the first and second multiplier-accumulation units are connected and operate together.

EFFECT: faster operation of the device and flexible simultaneous carrying out of different types of operations.

21 cl, 9 dwg