FUNCTIONAL INPUT STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER OF POSITION-SIGN SYSTEM f(+/-) FORMAT Russian patent published in 2010 - IPC G06F7/527

Abstract RU 2378684 C1

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices for carrying out arithmetic operations in position-sign codes. Each bit of the device is made in form of two structure-equivalent channels - positive and conditionally negative. In one version of implementation, the i^th bit of each channel contains two AND logic components and two NOR logic components.

EFFECT: faster operation of the device.

4 dwg

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RU 2 378 684 C1

Authors

Petrenko Lev Petrovich

Dates

2010-01-10—Published

2008-04-29—Filed