FUNCTIONAL STRUCTURE OF MULTIPLIER, IN WHICH INPUT ARGUMENTS HAVE FORMAT OF BINARY NUMERATION SYSTEM f(2), AND OUTPUT ARGUMENTS ARE FORMMED IN FORMAT OF POSITION-SIGN NUMERATION SYSTEM f(+/-) Russian patent published in 2009 - IPC G06F7/523

Abstract RU 2373563 C9

FIELD: information technologies.

SUBSTANCE: invention is related to computer engineering and may be used in building of arithmetical devices. Device comprises summator, at the outlet of which current sum ±[S_Σ]f(Δt)↓ and resulting sum ±[S_Σ] are formed in format of position-sign numeration system, two registers of opposite shift, two structures of logical elements AND, logical element AND, memory device.

EFFECT: improved efficiency.

1 dwg

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RU 2 373 563 C9

Authors

Petrenko Lev Petrovich

Dates

2009-11-20—Published

2008-04-29—Filed