FUNCTIONAL DESIGN OF PARALLEL POSITION-SIGN ADDER OF ARGUMENTS OF TERMS OF TWO FORMATS OF BINARY NUMBER SYSTEM f(2) AND POSITION-SIGN NUMBER SYSTEM f(+/-) (VERSIONS) Russian patent published in 2010 - IPC G06F7/505

Abstract RU 2390050 C2

FIELD: information technology.

SUBSTANCE: each bit of the adder in the first version contains three logic inverters, four AND logic elements and seven OR logic elements.

EFFECT: faster operation of the device.

8 cl, 30 dwg

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RU 2 390 050 C2

Authors

Petrenko Lev Petrovich

Dates

2010-05-20—Published

2008-04-29—Filed