METHOD OF PARALLEL BOOLEAN SUMMATION OF ANALOGUE SIGNALS OF TERMS EQUIVALENT TO BINARY NUMBER SYSTEM AND DEVICE FOR REALISING SAID METHOD Russian patent published in 2009 - IPC G06F7/50

Abstract RU 2375742 C2

FIELD: physics; computer engineering.

SUBSTANCE: invention relates to computer engineering and can be used in designing arithmetic devices and carrying out arithmetic operations, particularly summation and subtraction processes. Each bit of the device for parallel Boolean summation of arguments of analogue signals of terms equivalent to a position-sign number system f(+/-) is made in form of two equivalent channels for generating analogue signals of a positive and a conditionally negative sum +S_i and -S_i, each of which includes two AND elements, OR element, NOR element, NOT element.

EFFECT: faster summation.

2 cl, 6 dwg

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RU 2 375 742 C2

Authors

Petrenko Lev Petrovich

Dates

2009-12-10—Published

2006-12-15—Filed