FUNCTIONAL STRUCTURE OF PRE-ADDER f([m]&[m,0]) OF PARALLEL-SERIES MULTIPLIER f(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,m]f(2) and [m,0]f(2) (VERSIONS) Russian patent published in 2011 - IPC G06F7/505

Abstract RU 2424549 C1

FIELD: information technology.

SUBSTANCE: in one version of the invention, the functional structure in each bit contains elements executing logic functions OR, AND, NAND and NOR, wherein each bit is in form of two summation channels for generating a positive sum and a conditionally negative sum.

EFFECT: faster pre-summation process of a multiplicand in parallel-serial multiplier.

4 cl

Similar patents RU2424549C1

Title	Year	Author	Number
FUNCTIONAL STRUCTURE OF PARALLEL-SERIES MULTIPLIER f(Σ) IN POSITION FORMAT OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2)	2010	Petrenko Lev Petrovich	RU2439660C2
FUNCTIONAL STRUCTURE OF SELECTIVE LOGICAL DIFFERENTIATION OF ARGUMENTS OF BINARY SYSTEM FORMAT f(2)	2008	Petrenko Lev Petrovich	RU2373640C1
METHOD OF PARALLEL-SERIAL MULTIPLICATION OF POSITIONAL ARGUMENTS OF ANALOGUE SIGNALS OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2)	2010	Petrenko Lev Petrovich	RU2437142C2
FUNCTIONAL STRUCTURE OF PRE-ADDER f(Σ) OF CONDITIONAL "j" BIT OF PARALLEL-SERIAL MULTIPLIER f(Σ) IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF PARTIAL PRODUCTS WITH STRUCTURES OF ARGUMENTS OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE" AND FORMATION OF INTERMEDIATE SUM [Sj]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE RU" (RUSSIAN LOGIC VERSIONS)	2011	Petrenko Lev Petrovich	RU2586565C2
FUNCTIONAL STRUCTURES FOR PARALLEL-SERIAL RIPPLE CARRY f(←←)и f(←←) IN CONDITIONAL "i" "FORMATION ZONE" FOR CORRECTING RESULTANT PRELIMINARY FIRST LEVEL SUM OF ARGUMENTS OF PARTIAL PRODUCTS OF PARALLEL-SERIAL MULTIPLIER f(Σ) OF POSITIONAL FORMAT OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) (VERSIONS)	2010	Petrenko Lev Petrovich	RU2431886C1
FUNCTIONAL STRUCTURE FOR PRE-ADDER OF PARALLEL-SERIAL MULTIPLIER f(Σ) WITH MULTIPLICAND ARGUMENTS [m]f(2) AND MULTIPLIER ARGUMENTS [n]f(2) IN POSITION FORMAT (VERSIONS)	2010	Petrenko Lev Petrovich	RU2422879C1
METHOD OF GENERATING ARGUMENTS OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) OF ARGUMENTS OF MULTIPLIERS [m]f(2) И [n]f(2) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER f(Σ) FOR SUCCESSIVE LOGIC DECRYPTION f(CD↓) AND GENERATING RESULTANT SUM IN FORMAT [S]f(2) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)	2011	Petrenko Lev Petrovich	RU2473955C1
FUNCTIONAL STRUCTURE OF SERIAL RIPPLE CARRIES f(←←)and f(←←)OF CONDITIONAL "I" FORMATION ZONE FOR CORRECTING RESULTANT SUM OF PRESUMMATION OF ACTIVE ARGUMENTS OF MULTIPLICANT [m]f(2) OF POSITIONAL FORMAT IN PARALLEL-SERIAL MULTIPLIER f(Σ) (VERSIONS)	2010	Petrenko Lev Petrovich	RU2424550C1
METHOD OF GENERATING ORDERED SEQUENCES OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) OF ARGUMENTS OF MULTIPLIERS [n]f(2) AND [m]f(2) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER f(↓Σ) FOR SUCCESSIVE LOGIC DECRYPTION f(CD↓) AND GENERATING RESULTANT SUM IN FORMAT [S]f(2) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC)	2011	Petrenko Lev Petrovich	RU2463645C1
METHOD OF CONVERTING [m]f(+/-)→Uf([m]) MINIMISED STRUCTURE OF POSITION-SIGN ARGUMENTS [m]f(+/-) TERNARY NUMBER SYSTEM f(+1,0,-1) INTO ANALOGUE VOLTAGE ARGUMENT Uf([m]) (VERSION OF RUSSIAN LOGIC)	2012	Petrenko Lev Petrovich	RU2501160C1

RU 2 424 549 C1

Authors

Petrenko Lev Petrovich

Dates

2011-07-20—Published

2010-03-22—Filed