FIELD: information technologies.
SUBSTANCE: for every two conventionally "i" and "i+1" arguments of an analogue signal of a multiplier and analogue signals of positional structure of multiplier arguments, structures of analogue signals arguments of partial products are formed by linear logical structures AND1, AND2; the position structure of analogue signals of provisional sum is formed by means of a linear logical structure AND3 and is combined by means of a linear logical function AND1 for subsequent logical summation in the functional structure of a summator with a structure of arguments of analogue signals of intermediate sums of high-order digits, which is formed by means of combination by a linear logical function OR2 of intermediate sums of conventionally "i+2" and "i+3" arguments of an analogue signal of a multiplier and analogue signals of a positional structure of multiplicand arguments formed by means of linear logical structures AND4, AND5, AND6.
EFFECT: higher efficiency of multiplication operations performance.
