FUNCTIONAL STRUCTURE OF PRE-ADDER f(Σ) OF CONDITIONAL "j" BIT OF PARALLEL-SERIAL MULTIPLIER f(Σ) IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF PARTIAL PRODUCTS WITH STRUCTURES OF ARGUMENTS OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE" AND FORMATION OF INTERMEDIATE SUM [Sj]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE RU" (RUSSIAN LOGIC VERSIONS) Russian patent published in 2016 - IPC G06F7/505

Abstract RU 2586565 C2

FIELD: computer engineering.

SUBSTANCE: group of inventions relates to computer engineering and can be used in designing parallel-serial multiplier with input arguments of terms [m_j]f(2ⁿ) and [n_i]f(2ⁿ) in “complementary code” format. In one version, structure is realised using logic elements AND, OR, NOT, AND-NOT, OR-NOT.

EFFECT: high efficiency of converting input arguments.

2 cl

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RU 2 586 565 C2

Authors

Petrenko Lev Petrovich

Dates

2016-06-10—Published

2011-12-20—Filed