METHOD OF GENERATING ORDERED SEQUENCES OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) OF ARGUMENTS OF MULTIPLIERS [n]f(2) AND [m]f(2) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER f(↓Σ) FOR SUCCESSIVE LOGIC DECRYPTION f(CD↓) AND GENERATING RESULTANT SUM IN FORMAT [S]f(2) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC) Russian patent published in 2012 - IPC G06F7/527 

Abstract RU 2463645 C1

FIELD: information technology.

SUBSTANCE: one version, the structure is realised using logic elements AND, OR.

EFFECT: faster process of converting arguments of partial products in functional structures of multipliers.

5 cl

Similar patents RU2463645C1

Title Year Author Number
METHOD TO GENERATE ARGUMENTS OF ANALOG SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) ARGUMENTS OF MULTIPLICAND [m]f(2) AND ARGUMENTS OF MULTIPLIER [n]f(2) - "ADDITIONAL CODE" IN PYRAMIDAL MULTIPLIER f(↓Σ) FOR SUBSEQUENT LOGICAL DECODING f(CD↓) AND GENERATION OF RESULTING SUM IN FORMAT [S]f(2) -"ADDITIONAL CODE" AND FUNCTIONAL STRUCTURE FOR ITS REALISATION (VERSIONS OF RUSSIAN LOGICS) 2011
  • Petrenko Lev Petrovich
RU2481614C2
METHOD OF GENERATING ARGUMENTS OF ANALOGUE SIGNALS OF PARTIAL PRODUCTS [n]&[m]f(h) OF ARGUMENTS OF MULTIPLIERS [m]f(2) И [n]f(2) - "COMPLEMENTARY CODE" IN PYRAMIDAL MULTIPLIER f(Σ) FOR SUCCESSIVE LOGIC DECRYPTION f(CD↓) AND GENERATING RESULTANT SUM IN FORMAT [S]f(2) - "COMPLEMENTARY CODE" AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC) 2011
  • Petrenko Lev Petrovich
RU2473955C1
FUNCTIONAL STRUCTURE OF PRE-ADDER f(Σ) OF CONDITIONAL "j" BIT OF PARALLEL-SERIAL MULTIPLIER f(Σ) IMPLEMENTING PROCEDURE FOR "DECRYPTION" OF ARGUMENTS OF PARTIAL PRODUCTS WITH STRUCTURES OF ARGUMENTS OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE" AND FORMATION OF INTERMEDIATE SUM [Sj]f(2) IN POSITION FORMAT OF "ADDITIONAL CODE RU" (RUSSIAN LOGIC VERSIONS) 2011
  • Petrenko Lev Petrovich
RU2586565C2
METHOD OF PARALLEL-SERIAL MULTIPLICATION OF POSITIONAL ARGUMENTS OF ANALOGUE SIGNALS OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) 2010
  • Petrenko Lev Petrovich
RU2437142C2
METHOD OF CONVERTING [m]f(+/-)→Uf([m]) MINIMISED STRUCTURE OF POSITION-SIGN ARGUMENTS [m]f(+/-) TERNARY NUMBER SYSTEM f(+1,0,-1) INTO ANALOGUE VOLTAGE ARGUMENT Uf([m]) (VERSION OF RUSSIAN LOGIC) 2012
  • Petrenko Lev Petrovich
RU2501160C1
METHOD OF CONVERTING STRUCTURE OF ARGUMENTS OF ANALOGUE LOGIC VOLTAGES «-/+»[m]f(+/-) - "COMPLEMENTARY CODE" TO POSITION-SIGN STRUCTURE OF MINIMISED ARGUMENTS OF LOGIC VOLTAGES [m]f(+/-) AND FUNCTIONAL STRUCTURE FOR REALISATION THEREOF (VERSIONS OF RUSSIAN LOGIC) 2012
  • Petrenko Lev Petrovich
RU2502184C1
FUNCTIONAL OUTPUT STRUCTURE FOR PARALLEL-SERIAL MULTIPLIER f(Σ) IN POSITION FORMAT OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) (VERSIONS) 2010
  • Petrenko Lev Petrovich
RU2422881C1
FUNCTIONAL STRUCTURE OF PARALLEL-SERIES MULTIPLIER f(Σ) IN POSITION FORMAT OF MULTIPLICAND [m]f(2) AND MULTIPLIER [n]f(2) 2010
  • Petrenko Lev Petrovich
RU2439660C2
FUNCTIONAL STRUCTURE OF LEAST SIGNIFICANT BIT OF ADDER f(Σ) FOR ARGUMENTS OF TERMS [n]f(2) AND [m]f(2) OF "COMPLEMENTARY CODE RU" FORMAT (VERSIONS OF RUSSIAN LOGIC) 2012
  • Petrenko Lev Petrovich
RU2524562C2
FUNCTIONAL STRUCTURE OF PRE-ADDER f([m]&[m,0]) OF PARALLEL-SERIES MULTIPLIER f(Σ) WITH PROCEDURE FOR LOGIC DIFFERENTIATION d/dn OF FIRST INTERMEDIATE SUM [S ]f(})- OR STRUCTURE OF ACTIVE ARGUMENTS OF MULTIPLICAND [0,m]f(2) and [m,0]f(2) (VERSIONS) 2010
  • Petrenko Lev Petrovich
RU2424549C1

RU 2 463 645 C1

Authors

Petrenko Lev Petrovich

Dates

2012-10-10Published

2011-05-04Filed